The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 2024

Filed:

Dec. 10, 2021
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventor:

Shingo Nakazawa, Kamakura, JP;

Assignee:

KIOXIA CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/16 (2006.01); G11C 16/34 (2006.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01);
U.S. Cl.
CPC ...
G11C 16/16 (2013.01); G11C 16/3445 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02);
Abstract

A semiconductor memory device includes first conductive layers, second conductive layers, a first semiconductor layer, a charge storage layer, and a first wiring. The semiconductor memory device is configured to execute an erase operation including a first and a second erase loop. In the first erase loop, the semiconductor memory device applies a first voltage to at least a part of the first conductive layers and at least a part of the second conductive layers and applies an erase voltage larger than the first voltage to the first wiring. In the second erase loop, the semiconductor memory device applies the first voltage to at least a part of the first conductive layers, applies a second voltage larger than the first voltage to at least apart of the second conductive layers, and applies the erase voltage to the first wiring.


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