The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 2024

Filed:

Nov. 23, 2021
Applicants:

Mahesh Balasubramanian, Tempe, AZ (US);

Aviral Shrivastava, Phoenix, AZ (US);

Inventors:

Mahesh Balasubramanian, Tempe, AZ (US);

Aviral Shrivastava, Phoenix, AZ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 9/445 (2018.01);
U.S. Cl.
CPC ...
G06F 9/30065 (2013.01); G06F 9/3001 (2013.01); G06F 9/44505 (2013.01);
Abstract

Various embodiments of a system and associated method for generating a valid mapping for a computational loop on a CGRA are disclosed herein. In particular, the method includes generating randomized schedules within particular constraints to explore greater mapping spaces than previous approaches. Further, the system and related method employs a feasibility test to test validity of each schedule such that mappings are only generated from valid schedules.


Find Patent Forward Citations

Balasubramanian, Mahesh. (2024). Systems and methods for improved mapping of computational loops on reconfigurable architectures (U.S. Patent No. 11928468). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11928468

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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