The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 12, 2024
Filed:
Mar. 30, 2022
National Technology & Engineering Solutions of Sandia, Llc, Albuquerque, NM (US);
Jason P. Krein, Albuquerque, NM (US);
Jeremy W. Giron, Albuquerque, NM (US);
Matthew S. Geuss, Albuquerque, NM (US);
Robert Nevett, IV, Albuquerque, NM (US);
Stephen T. Simpson, Albuquerque, NM (US);
Roger Martin Kilgore, Placitas, NM (US);
Jacob Edward Leemaster, Cambridge, MA (US);
National Technology & Engineering Solutions of Sandia, LLC, Albuquerque, NM (US);
Abstract
A fault insertion device (FID) comprises a transceiver and an FPGA. The transceiver receives signals from a MIL-STD-1553/1760 communications bus. The FPGA evaluates the signals received from the communications bus against a set of rules stored by the FPGA. Based upon the set of rules, the FPGA can selectively modify messages received from the communications bus prior to transmission to a remote terminal or a bus controller that is configured to communicate on the communications bus.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile