The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2024

Filed:

Jan. 26, 2023
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Hongtao Zhang, San Jose, CA (US);

Ankur Jain, Sunnyvale, CA (US);

Yanfei Chen, Cupertino, CA (US);

Ronan Sean Casey, Cork, IE;

Winson Lin, San Francisco, CA (US);

Hsung Jai Im, San Jose, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/08 (2006.01); H03L 7/099 (2006.01); H03M 1/82 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0802 (2013.01); H03L 7/0991 (2013.01); H03M 1/82 (2013.01);
Abstract

Embodiments herein describe correcting nonlinearity in a Digital-to-Time Converter (DTC) by relaxing a DTC linearity requirement, which results in the correction being co-adapted with a DTC gain calibration loop which can operate in parallel with a DTC integral nonlinearity (INL) correction loop. In one embodiment, the DTC gain calibration loop and the DTC INL correction loop are constrained when determining a nonlinearity correction code to improve the likelihood they converge. Once determined, the nonlinearity correction code can be combined with an digital code output by a time-to-digital converter (TDC) to generate a phase difference between a reference clock and a feedback clock.


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