The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2024

Filed:

Apr. 05, 2022
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Bob W. Verbruggen, Dublin, IE;

Christophe Erdmann, Nice, FR;

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/00 (2006.01); H03K 5/135 (2006.01); H03K 5/14 (2014.01); H03K 5/15 (2006.01); H03K 19/0948 (2006.01); H03M 1/82 (2006.01);
U.S. Cl.
CPC ...
H03K 5/14 (2013.01); H03K 5/135 (2013.01); H03K 5/15066 (2013.01); H03K 19/0948 (2013.01); H03M 1/82 (2013.01); H03K 2005/00026 (2013.01);
Abstract

Methods and apparatus for time-to-digital conversion. An example apparatus includes a first input; a second input; a delay line coupled to the first input and comprising a plurality of first delay elements coupled in series, each of the plurality of first delay elements having a first delay time; a second delay element having an input coupled to the second input and having the first delay time; a third delay element having an input coupled to the second input and having a second delay time, the second delay time being smaller than the first delay time; a first set of arbiters having first inputs coupled to the delay line and having second inputs coupled to an output of the second delay element; and a second set of arbiters having first inputs coupled to the delay line and having second inputs coupled to an output of the third delay element.


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