The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 05, 2024
Filed:
Apr. 12, 2022
Applicant:
Canon Kabushiki Kaisha, Tokyo, JP;
Inventors:
Kohichi Nakamura, Kanagawa, JP;
Yasuhiro Oguro, Tokyo, JP;
Assignee:
CANON KABUSHIKI KAISHA, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/037 (2006.01); G06T 7/55 (2017.01); H04N 25/71 (2023.01); H03L 7/08 (2006.01); H03M 9/00 (2006.01);
U.S. Cl.
CPC ...
H03K 3/037 (2013.01); G06T 7/55 (2017.01); H04N 25/745 (2023.01); G06T 2207/30252 (2013.01); H03L 7/08 (2013.01); H03M 9/00 (2013.01);
Abstract
Provided is a logic circuit including a first circuit including a static D flip-flop and a second circuit including a dynamic D flip-flop. The first circuit receives a clock signal and a first reset signal. The first circuit outputs a second reset signal generated by synchronizing the first reset signal with the clock signal. The second circuit receives the clock signal and a signal based on the second reset signal.