The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2024

Filed:

Apr. 07, 2021
Applicant:

Gowin Semiconductor Corporation, GuangZhou, CN;

Inventors:

Jinghui Zhu, San Jose, CA (US);

Jiyong Zhang, Jinan, CN;

Jianhua Liu, Fremont, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3185 (2006.01); G01R 31/302 (2006.01); H03K 19/17728 (2020.01); H03K 19/17758 (2020.01);
U.S. Cl.
CPC ...
H03K 19/17758 (2020.01); G01R 31/3025 (2013.01); G01R 31/318519 (2013.01); G01R 31/318597 (2013.01); H03K 19/17728 (2013.01);
Abstract

A programmable semiconductor device contains a wireless communication block ('WCB') capable of facilitating wirelessly field programmable gate array (“FPGA”) programming download as well as functional logic implementation. In one aspect, WCB detects an FPGA access request for initiating an FPGA reconfiguration from a remote system via a wireless communications network. Upon receiving a configuration bitstream for programming the FPGA via the wireless communications network, the configuration bitstream is forwarded from WCB to a configuration download block (“CDB”) for initiating a configuration process. CDB subsequently programs at least a portion of configurable logic blocks (“LBs”) in FPGA in response to the configuration bitstream.


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