The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 05, 2024
Filed:
Jun. 17, 2022
Applicant:
Psemi Corporation, San Diego, CA (US);
Inventors:
Alper Genc, San Diego, CA (US);
Peter Bacon, New Hampshire, CT (US);
Assignee:
PSEMI CORPORATION, San Diego, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/687 (2006.01); H03K 17/06 (2006.01); H03K 17/10 (2006.01);
U.S. Cl.
CPC ...
H03K 17/687 (2013.01); H03K 17/06 (2013.01); H03K 17/102 (2013.01); H03K 2017/066 (2013.01);
Abstract
Methods and devices to reduce the gate-induced drain/body leakage current (GIDL) generated in FET switch stacks when in OFF state are disclosed. Such devices include inductors as part of bias networks coupled with drain/source terminals and/or body terminals of the transistors within the switch stack. Hybrid approaches where resistors in combination with inductors are implemented as part the bias network are also described.