The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 05, 2024
Filed:
Nov. 17, 2020
Applicant:
Stmicroelectronics (Tours) Sas, Tours, FR;
Inventor:
Ludovic Fallourd, Louans, FR;
Assignee:
STMicroelectronics (Tours) SAS, Tours, FR;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 21/56 (2006.01); H01L 21/762 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/367 (2006.01); H01L 23/495 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 21/76224 (2013.01); H01L 21/0228 (2013.01); H01L 21/56 (2013.01);
Abstract
The present disclosure relates to a method for manufacturing electronic chips. The method includes forming a plurality of trenches on a first face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed. The trenches delimit laterally a plurality of chips, and each of the chips includes a single integrated circuit. The method further includes electrically isolating flanks of each of the chips by forming an electrically isolating layer on lateral walls of the trenches.