The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2024

Filed:

Jan. 21, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Sangwoo Kim, Seoul, KR;

Younghoon Son, Yongin-si, KR;

Seongheon Yu, Yongin-si, KR;

Joungyeal Kim, Yongin-si, KR;

Chulung Kim, Seou, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/22 (2006.01); G11C 7/10 (2006.01); G11C 29/12 (2006.01); G11C 29/46 (2006.01);
U.S. Cl.
CPC ...
G11C 7/222 (2013.01); G11C 7/1069 (2013.01); G11C 7/1096 (2013.01); G11C 29/12015 (2013.01); G11C 29/46 (2013.01);
Abstract

An apparatus includes a host and a memory device connected to the host through a bus. The bus is used to communicate a data clock controlling data write timing during a write operation executed by the memory device and a read clock controlling data read timing during a read operation executed by the memory device. The memory device performs first duty cycle monitoring that monitors a duty cycle of the data clock, generates a first result, and provides a timing-adjusted data clock, performs second duty cycle monitoring that monitors a duty cycle of the read clock, generates a second result, and provides a timing-adjusted read clock, calculates an offset of the read clock based on the timing-adjusted data clock, the result and the second result, and corrects a duty error of the read clock using a read clock offset code derived from the offset of the read clock.


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