The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2024

Filed:

Feb. 08, 2021
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Adam P. Donlin, San Jose, CA (US);

Kyle Corbett, Campbell, CA (US);

Lizhi Hou, Santa Clara, CA (US);

Julian M. Kain, Longmont, CO (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01); G06F 9/38 (2018.01); H04L 9/06 (2006.01);
U.S. Cl.
CPC ...
G06F 9/5077 (2013.01); G06F 9/3836 (2013.01); G06F 9/3877 (2013.01); H04L 9/0643 (2013.01);
Abstract

Control of a reconfigurable platform can include determining, by a host computer, an interface universally unique identifier (UUID) of an interface of platform circuitry implemented on an accelerator, wherein the accelerator is communicatively linked to the host computer. An electronic request to run a partition design on the accelerator is received by the host computer. In response to the electronic request, the host computer determines an interface UUID for an interface of the partition design and determines compatibility of the partition design with the platform circuitry based on a comparison of the interface UUID of the partition design with the interface UUID of the platform circuitry. The partition design is implemented on the accelerator in response to determining that the partition design is compatible with the platform circuitry.


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