The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 05, 2024
Filed:
Apr. 27, 2022
Seagate Technology Llc, Fremont, CA (US);
Jon D. Trantham, Chanhassen, MN (US);
Praveen Viraraghavan, Chicago, IL (US);
John W. Dykes, Eden Prairie, MN (US);
Ian J. Gilbert, Chanhassen, MN (US);
Sangita Shreedharan Kalarickal, Eden Prairie, MN (US);
Matthew J. Totin, Excelsior, MN (US);
Mohamad El-Batal, Superior, CO (US);
Darshana H. Mehta, Shakopee, MN (US);
SEAGATE TECHNOLOGY LLC, Fremont, CA (US);
Abstract
Apparatus and method for managing data in a processing system, such as but not limited to a data storage device such as a solid-state drive (SSD). A ferroelectric stack register memory has a first arrangement of ferroelectric memory cells (FMEs) of a first construction and a second arrangement of FMEs of a different, second construction arranged to provide respective cache lines for use by a controller, such as a programmable processor. A pointer mechanism is configured to provide pointers to point to each of the respective cache lines based on a time sequence of operation of the processor. Data sets can be migrated to the different arrangements by the controller as required based on the different operational characteristics of the respective FME constructions. The FMEs may be non-volatile and read-destructive. Refresh circuitry can be selectively enacted under different operational modes.