The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 27, 2024

Filed:

Dec. 29, 2022
Applicant:

Sambanova Systems, Inc., Palo Alto, CA (US);

Inventors:

Fahim Ur Rahman, Ruston, LA (US);

Jinuk Shin, San Jose, CA (US);

Assignee:

SambaNova Systems, Inc., Palo Alto, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/10 (2006.01); H03H 17/02 (2006.01); H03L 7/081 (2006.01); H03L 7/093 (2006.01); H03H 17/00 (2006.01);
U.S. Cl.
CPC ...
H03L 7/10 (2013.01); H03H 17/02 (2013.01); H03L 7/0812 (2013.01); H03L 7/093 (2013.01); H03H 2017/0081 (2013.01);
Abstract

A DLL includes a delay line with two phase outputs, a gater coupled with the delay line phase outputs, a PFD coupled with gater outputs, a PD coupled with PFD outputs, a retimer coupled with PD outputs, and a loop filter with inputs coupled with the retimer and a speed control output coupled with the delay line. The gater passes signals on its two inputs to its two outputs, apart from a first pulse on its first input. The PD determines if the second gated signal leads or lags the first gated signal. The retimer retimes PD output signals to be aligned with a delay line input signal. The loop filter uses the retimed PD output signals to determine if the delay line should delay more or delay less, and outputs a speed control signal to control the delay line speed.


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