The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 27, 2024

Filed:

Dec. 13, 2022
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Yong Xu, San Diego, CA (US);

Boris Dimitrov Andreev, San Diego, CA (US);

Vikas Mahendiyan, San Diego, CA (US);

Yuxin Li, San Diego, CA (US);

Anand Meruva, San Diego, CA (US);

Jeffrey Mark Hinrichs, San Diego, CA (US);

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/00 (2006.01); G06F 1/12 (2006.01); H03K 19/20 (2006.01); H03L 7/081 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0812 (2013.01); G06F 1/12 (2013.01); H03K 19/20 (2013.01);
Abstract

A method for clock switching includes propagating a first clock signal through a first clock path, propagating a second clock signal through a second clock path, generating a first delay control signal based on the first clock signal, and generating a second delay control signal based on the second clock signal. The method also includes, in a first mode, coupling the first clock path to a delay circuit and inputting the first delay control signal to a control input of the delay circuit. The method also includes, in a second mode, coupling the second clock path to the delay circuit and inputting the second delay control signal to the control input of the delay circuit.


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