The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 27, 2024

Filed:

Dec. 20, 2019
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Xianzhi Dai, Shanghai, CN;

Rajkumar Sankaralingam, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H02H 9/04 (2006.01); H01L 27/02 (2006.01); H02H 3/20 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0266 (2013.01); H02H 3/20 (2013.01); H02H 9/04 (2013.01); H02H 9/041 (2013.01); H01L 27/0285 (2013.01);
Abstract

A microelectronic device has a protected line and a reference line, and an active field effect transistor (FET) coupled between the protected line and the reference line. The microelectronic device includes an electrostatic discharge (ESD) trigger circuit coupled to the gate of the active FET, to turn on the active FET when an ESD event occurs on the protected line. The microelectronic device further includes a transient detection circuit having a high bandwidth detector, an ESD detector, and an output driver. The ESD detector is configured to provide a CLEAR signal to the output driver when an ESD event occurs on the protected line. The output driver is configured to turn off the active FET when a voltage surge, which can damage the active FET, occurs on the protected line, but enable operation of the active FET by the ESD trigger circuit during an ESD event.


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