The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 27, 2024
Filed:
Oct. 18, 2019
Daicel Corporation, Osaka, JP;
Naoko Tsuji, Tokyo, JP;
DAICEL CORPORATION, Osaka, JP;
Abstract
An object of the present invention is to provide a technique suitable for achieving low wiring resistance and reducing a variation in the resistance value between semiconductor elements to be multilayered in a method of manufacturing a semiconductor device in which the semiconductor elements are multilayered through laminating semiconductor wafers via an adhesive layer. The method of the present invention includes first to third processes. In the first process, a wafer laminate Y is prepared, the wafer laminate Y having a laminated structure including a wafer, wafersT with a thickness from 1 to 20 um, and an adhesive layerwith a thickness from 0.5 to 4.5 μm interposed between a main surfaceof the waferand a back surfaceof the waferT. In the second process, holes extending from the main surfaceof the waferT and reaching a wiring pattern of the waferare formed by a predetermined etching treatment. In the third process, the holes are filled with a conductive material to form through electrodes. The adhesive layerhas an etching rate of 1 to 2 μm/min in dry etching performed using an etching gas containing CF, O, and Ar at a volume ratio of 100:400:200 under predetermined conditions.