The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 27, 2024

Filed:

Mar. 01, 2022
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Adrian Montero, Austin, TX (US);

Huzefa Sanjeliwala, Austin, TX (US);

Paul Kitchin, Austin, TX (US);

Prarthna Santhanakrishnan, Austin, TX (US);

Conrado Blasco, San Mateo, CA (US);

Pradeep Kanapathipillai, Campbell, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/1036 (2016.01); G06F 9/30 (2018.01); G06F 9/455 (2018.01);
U.S. Cl.
CPC ...
G06F 12/1036 (2013.01); G06F 9/30043 (2013.01); G06F 9/30047 (2013.01); G06F 9/30087 (2013.01); G06F 9/45558 (2013.01); G06F 2009/45562 (2013.01);
Abstract

An electronic device includes one or more processors for executing one or more virtual machines. In response to a request for initiating a synchronization event, a processor identifies a subset of speculative memory access requests in one or more memory access request queues. Automatically and in accordance with the identifying, the processor purges translations associated with the subset of speculative memory access requests. Subsequent to the purging, the processor initiates the synchronization event. In some implementations, memory access completion is forced in response to a context synchronization event that corresponds to a termination of a first application, a termination of a first virtual machine, or a system call for updating a system register. Alternatively, in some implementations, memory access completion is forced in an operating system level or an application level in response to a data synchronization event that is initiated on a hypervisor layer or a firmware layer.


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