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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11910614 B1

PDFFull Text
Date of Patent:
Feb. 20, 2024

Filed:

Apr. 01, 2022

Three dimensional semiconductor device and method of forming the same

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Chang Sup Lee, Hwaseong-si, KR;

Phil Ouk Nam, Suwon-si, KR;

Sung Yun Lee, Seongnam-si, KR;

Chang Seok Kang, Seongnam-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, KR;

Attorney:

Muir Patent Law, PLLC

Primary Examiner:

Matthew E Warren

Int. Cl.
CPC ...
H10B 43/50 (2023.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H10B 41/27 (2023.01); H10B 41/50 (2023.01); H10B 43/10 (2023.01); H10B 43/20 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01);
U.S. Cl.
CPC ...
H10B 43/50 (2023.02); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/53295 (2013.01); H10B 41/27 (2023.02); H10B 41/50 (2023.02); H10B 43/10 (2023.02); H10B 43/20 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02);
Abstract

A three-dimensional semiconductor device and a method of forming the same are provided. The three-dimensional semiconductor device comprises a substrate including first and second areas; first and second main separation patterns, disposed on the substrate and intersecting the first and second areas; gate electrodes disposed between the first and second main separation patterns and forming a stacked gate group, the gate electrodes sequentially stacked on the first area and extending in a direction from the first area to the second area; and at least one secondary separation pattern disposed on the second area, disposed between the first and second main separation patterns, and penetrating through the gate electrodes disposed on the second area. The gate electrodes include pad portions on the second area, and the pad portions are thicker than the gate electrodes disposed on the first area and in contact with the at least one secondary separation pattern.

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