The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2024

Filed:

Jul. 27, 2020
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Inventors:

Munehiro Kozuma, Kanagawa, JP;

Takahiko Ishizu, Kanagawa, JP;

Takeshi Aoki, Kanagawa, JP;

Masashi Fujita, Tokyo, JP;

Kazuma Furutani, Kanagawa, JP;

Kousuke Sasaki, Kanagawa, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); H01L 29/786 (2006.01); G06F 7/544 (2006.01); G11C 7/12 (2006.01); G11C 7/14 (2006.01); H10B 12/00 (2023.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7869 (2013.01); G06F 7/5443 (2013.01); G11C 7/1069 (2013.01); G11C 7/1096 (2013.01); G11C 7/12 (2013.01); G11C 7/14 (2013.01); H10B 12/50 (2023.02); H01L 27/1225 (2013.01);
Abstract

A semiconductor device having a novel structure is provided. The semiconductor device includes a CPU and an accelerator. The accelerator includes a first memory circuit and an arithmetic circuit. The first memory circuit includes a first transistor. The first transistor includes a semiconductor layer containing a metal oxide in a channel formation region. The arithmetic circuit includes a second transistor. The second transistor includes a semiconductor layer containing silicon in a channel formation region. The first transistor and the second transistor are provided to be stacked. The CPU includes a CPU core including a flip-flop provided with a backup circuit. The backup circuit includes a third transistor. The third transistor includes a semiconductor layer containing a metal oxide in a channel formation region.


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