The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2024

Filed:

Dec. 05, 2019
Applicant:

Suzhou Oriental Semiconductor Co., Ltd., Suzhou, CN;

Inventors:

Yi Gong, Jiangsu, CN;

Wei Liu, Jiangsu, CN;

Yuanlin Yuan, Jiangsu, CN;

Lei Liu, Jiangsu, CN;

Rui Wang, Jiangsu, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 27/06 (2006.01); H01L 29/88 (2006.01); H01L 29/78 (2006.01); H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0634 (2013.01); H01L 27/0629 (2013.01); H01L 29/788 (2013.01);
Abstract

Provided is a semiconductor super junction power device. The semiconductor super junction power device includes an MOSFET cell array composed of multiple super junction MOSFET cells. Each of multiple MOSFET cells includes a p-type body region located at the top of an n-type drift region, a p-type columnar doping region located below the p-type body region, an n-type source region located in the p-type body region, a gate dielectric layer located above the p-type body region, a gate electrode located above the p-type body region, an n-type floating gate located above the p-type body region and an opening located in the gate dielectric layer, where in a lateral direction, the gate electrode is located on one side close to the n-type source region; an opening located in the gate dielectric layer, where the n-type floating gate contacts the p-type body region through the opening to form a p-n junction diode.


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