The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2024

Filed:

Oct. 22, 2019
Applicant:

Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Wuhan, CN;

Inventors:

Xing Ming, Wuhan, CN;

Zhongtao Cao, Wuhan, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H10K 77/10 (2023.01); H10K 59/123 (2023.01); H10K 102/00 (2023.01); H10K 59/12 (2023.01);
U.S. Cl.
CPC ...
H01L 27/1218 (2013.01); H10K 59/123 (2023.02); H10K 77/111 (2023.02); H10K 59/1201 (2023.02); H10K 2102/311 (2023.02);
Abstract

A TFT array substrate includes a substrate layer and a metal layer disposed on the substrate layer. The metal layer includes a metal layer bridging structure having a first metal layer and a bridging second metal layer. An insulating layer is disposed between the first metal layer and the bridging second metal layer. The first metal layer includes two segments of a first segment and a second segment of the first metal layer, which are disposed at intervals. The first segment and the second segment of the first metal layer are connected by the bridging second metal layer. The TFT array substrate has a bending region adopting a new metal layer routing structure, and routing of the first metal layer in the bending region is prevented from passing through two holes of a filling layer (OILD), thereby effectively reducing the risk of subsequent breakage due to over-etching.


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