The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2024

Filed:

Jul. 24, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Sung Soo Kim, Seoul, KR;

Gi Gwan Park, Suwon-si, KR;

Jung Hun Choi, Seoul, KR;

Koung Min Ryu, Hwaseong-si, KR;

Sun Jung Lee, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 23/485 (2006.01); H01L 23/528 (2006.01); H01L 29/423 (2006.01); H01L 27/092 (2006.01); H01L 29/739 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); H01L 21/823431 (2013.01); H01L 21/823456 (2013.01); H01L 21/823475 (2013.01); H01L 23/485 (2013.01); H01L 23/5283 (2013.01); H01L 29/42364 (2013.01); H01L 29/42372 (2013.01); H01L 27/0924 (2013.01); H01L 29/7391 (2013.01);
Abstract

A semiconductor device includes a substrate including a first region, and a second region, a first gate structure and a second gate structure on the substrate of the first region, a third gate structure and a fourth gate structure on the substrate of the second region, a first interlayer insulating film on the substrate of the first region and including a first lower interlayer insulating film and a first upper interlayer insulating film, a second interlayer insulating film on the substrate of the second region and including a second lower interlayer insulating film and a second upper interlayer insulating film, a first contact between the first gate structure and the second gate structure and within the first interlayer insulating film, and a second contact formed between the third gate structure and the fourth gate structure and within the second interlayer insulating film.


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