The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2024

Filed:

Aug. 04, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Seonah Nam, Yongin-si, KR;

Byungju Kang, Seoul, KR;

Byungsung Kim, Suwon-si, KR;

Hyelim Kim, Asan-si, KR;

Sungho Park, Suwon-si, KR;

Yubo Qian, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 23/538 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); B82Y 10/00 (2011.01); H01L 21/8234 (2006.01); H01L 29/417 (2006.01); H01L 27/02 (2006.01); H01L 29/775 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/088 (2013.01); H01L 23/5384 (2013.01); H01L 29/0653 (2013.01); H01L 29/4232 (2013.01);
Abstract

A semiconductor device includes first and second external dummy areas, and a circuit area between the first and second external dummy areas. The circuit area includes circuit active regions and circuit gate lines. Each external dummy area includes an external dummy active region and external dummy gate lines overlapping the external dummy active region and spaced apart from the circuit gate lines. The external dummy active region has a linear shape extending in a first horizontal direction or a shape including active portions isolated from direct contact with each other and extending sequentially in the first horizontal direction. The circuit active regions are between the first and second external dummy active regions and include a first plurality of circuit active regions extending sequentially in the first horizontal direction and a second plurality of circuit active regions extending sequentially in a second horizontal direction perpendicular to the first horizontal direction.


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