Semiconductor memory device and memory system having the same

Abstract

A semiconductor memory device includes a command and address generator configured to decode a command to generate an active command, and generate an address applied with the active command as a row address, a control signal generator configured to generate sequence data changing with a random sequence in response to the active command, and generate a random pick signal when the sequence data is equal to previously stored comparison data, and a memory cell array comprising an odd page memory cell array including a plurality of first memory cells and an even page memory cell array including a plurality of second memory cells, and configured to simultaneously perform the active operation and a hidden hammer refresh operation on the selected first and second memory cells in response to the row address when the random pick signal is activated in response to the active command.