The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 20, 2024
Filed:
Apr. 13, 2022
Seagate Technology Llc, Fremont, CA (US);
Jon D. Trantham, Chanhassen, MN (US);
Praveen Viraraghavan, Chicago, IL (US);
John W. Dykes, Eden Prairie, MN (US);
Ian J. Gilbert, Chanhassen, MN (US);
Sangita Shreedharan Kalarickal, Eden Prairie, MN (US);
Matthew J. Totin, Excelsior, MN (US);
Mohamad El-Batal, Superior, CO (US);
Darshana H. Mehta, Shakopee, MN (US);
SEAGATE TECHNOLOGY LLC, Fremont, CA (US);
Abstract
A memory device formed of ferroelectric field effect transistors (FeFETs). The memory device can be used as a front end buffer, such as in a data storage device having a non-volatile memory (NVM). A controller can be configured to transfer user data between the NVM and an external client (host) via the buffer. The FeFETs can be arranged in a two-dimensional (2D) or a three-dimensional (3D) array. A monitor circuit can be used to monitor operation of the FeFETs. An optimization controller can be used to adjust at least one operational parameter associated with the FeFETs responsive to the monitored operation by the monitor circuit. The FeFETs may require a refresh operation after each read operation. A power down sequence can involve a read operation without a subsequent refresh operation to wipe the FeFETs, the read operation jettisoning the data read from the buffer memory.