The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2024

Filed:

Aug. 02, 2018
Applicant:

Hamamatsu Photonics K.k., Hamamatsu, JP;

Inventors:

Tatsuya Sugimoto, Hamamatsu, JP;

Tomofumi Suzuki, Hamamatsu, JP;

Kyosuke Kotani, Hamamatsu, JP;

Yutaka Kuramoto, Hamamatsu, JP;

Daiki Suzuki, Hamamatsu, JP;

Assignee:

HAMAMATSU PHOTONICS K.K., Hamamatsu, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B81C 1/00 (2006.01); G02B 26/10 (2006.01); G02B 7/182 (2021.01); G02B 26/08 (2006.01); H02N 1/00 (2006.01);
U.S. Cl.
CPC ...
G02B 26/0841 (2013.01); B81C 1/00555 (2013.01); G02B 7/1821 (2013.01); G02B 26/105 (2013.01); H02N 1/008 (2013.01); B81B 2201/042 (2013.01); B81C 2201/013 (2013.01); B81C 2201/0174 (2013.01); B81C 2201/0198 (2013.01);
Abstract

A method for manufacturing an optical device includes: preparing a semiconductor substrate that includes a portion corresponding to a base, a movable unit, and an elastic support portion; forming a first resist layer in a region corresponding to the base on a surface of a first semiconductor layer which is opposite to an insulating layer; forming a depression in the first semiconductor layer by etching the first semiconductor layer using the first resist layer as a mask; forming a second resist layer in a region corresponding to a rib portion on a bottom surface of the depression, a side surface of the depression, and the surface of the first semiconductor layer which is opposite to the insulating layer; and forming the rib portion by etching the first semiconductor layer until reaching the insulating layer using the second resist layer as a mask.


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