The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 20, 2024
Filed:
Oct. 18, 2021
Applicant:
Stmicroelectronics (Rousset) Sas, Rousset, FR;
Inventor:
Pascal Fornara, Pourrieres, FR;
Assignee:
STMicroelectronics (Rousset) SAS, Rousset, FR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01D 5/24 (2006.01); H01L 27/06 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H01L 21/28 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
G01D 5/24 (2013.01); H01L 27/0629 (2013.01); H01L 28/60 (2013.01); H01L 29/40114 (2019.08); H01L 29/66765 (2013.01); H01L 29/78678 (2013.01);
Abstract
An integrated circuit includes a first substrate. A MOS transistor has a first polysilicon region electrically isolated from the first substrate and including a gate region. A second polysilicon region is electrically isolated from the first polysilicon region and from the first substrate. The second polysilicon region includes a source region, a substrate region and a drain region of the MOS transistor. The first polysilicon region is located between an area of the first substrate and the second polysilicon region.