The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2024

Filed:

Oct. 12, 2020
Applicants:

Chengdu Boe Optoelectronics Technology Co., Ltd., Sichuan, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Zhen Zhang, Beijing, CN;

Ning Zhao, Beijing, CN;

Xinwei Wu, Beijing, CN;

Xudong An, Beijing, CN;

Yue Wei, Beijing, CN;

Yuqing Yang, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/32 (2006.01); H10K 59/131 (2023.01); H10K 50/84 (2023.01); H10K 59/124 (2023.01); H10K 71/00 (2023.01); H10K 59/12 (2023.01);
U.S. Cl.
CPC ...
H10K 59/131 (2023.02); H10K 50/84 (2023.02); H10K 59/124 (2023.02); H10K 71/00 (2023.02); H10K 59/1201 (2023.02);
Abstract

Provided are a display panel, a manufacturing method therefor, and a display device. The display panel comprises a hole in a display region and comprises: a substrate; a drive circuit layer comprising a thin film transistor; a wire, connected to the thin film transistor; one or more isolation members surrounding the hole, disposed on the side of the drive circuit layer, and located between the wire and the hole, at least one isolation member comprising a first and a second isolation layer, and an orthographic projection of a surface of the first isolation layer away from the substrate is inside that of the second isolation layer on the substrate; a planarization layer, on the side of the drive circuit layer and covering the wire; and an anode, on the side of the planarization layer and connected to the wire by a via penetrating the planarization layer.


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