The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2024

Filed:

May. 06, 2022
Applicant:

Samsung Display Co., Ltd., Yongin-si, KR;

Inventors:

Ji Eun Choi, Seoul, KR;

Deok Hoi Kim, Seongnam-si, KR;

Jeong Hwan Kim, Cheonan-si, KR;

Jong Baek Seon, Yongin-si, KR;

Jun Cheol Shin, Asan-si, KR;

Jae Hak Lee, Yongin-si, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10K 59/12 (2023.01); H10K 59/121 (2023.01); H10K 59/123 (2023.01); H10K 59/126 (2023.01); H10K 77/10 (2023.01); H01L 27/12 (2006.01); H01L 29/24 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H10K 102/00 (2023.01);
U.S. Cl.
CPC ...
H10K 59/1213 (2023.02); H10K 59/123 (2023.02); H10K 59/126 (2023.02); H10K 59/1216 (2023.02); H10K 77/111 (2023.02); H01L 27/1225 (2013.01); H01L 27/1251 (2013.01); H01L 27/1255 (2013.01); H01L 27/1259 (2013.01); H01L 29/24 (2013.01); H01L 29/66757 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/78633 (2013.01); H01L 29/78648 (2013.01); H01L 29/78675 (2013.01); H10K 59/1201 (2023.02); H10K 2102/311 (2023.02);
Abstract

A display device includes: a base substrate having a display region including a first region and a second region, and a non-display region; a first semiconductor layer including polysilicon at the second region; a first conductive layer on a first insulating layer, and including a bottom gate electrode at the first region and a second-first gate electrode at the second region; a second semiconductor layer including an oxide on a second insulating layer at the first region; a second conductive layer on a third insulating layer, and including a top gate electrode at the first region and a second-second gate electrode at the second region; and a third conductive layer on a fourth insulating layer, and including a first source electrode and a first drain electrode connected to the second semiconductor layer, and a second source electrode and a second drain electrode connected to the first semiconductor layer.


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