The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2024

Filed:

Jun. 29, 2021
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Yu Jeong Lee, Icheon-si, KR;

Dae Hwan Yun, Icheon-si, KR;

Gil Bok Choi, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); H10B 41/27 (2023.01); H01L 23/31 (2006.01); H01L 29/04 (2006.01); H01L 29/16 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H01L 21/02164 (2013.01); H01L 21/02238 (2013.01); H01L 21/02532 (2013.01); H01L 21/02592 (2013.01); H01L 21/02667 (2013.01); H01L 23/3171 (2013.01); H01L 29/04 (2013.01); H01L 29/16 (2013.01);
Abstract

A semiconductor memory device may include a core pillar extended in a vertical direction, a channel layer having a first region covering a portion of a side surface of the core pillar and a second region covering the other portion of the side surface of the core pillar and a bottom surface of the core pillar, the second region abutting the first region, and a channel passivation layer formed in the first region of the channel layer and abutting the core pillar.


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