The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2024

Filed:

Sep. 19, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Hongbo Si, Plano, TX (US);

Young-Han Nam, Plano, TX (US);

Youngbum Kim, Seoul, KR;

Taehyoung Kim, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 5/00 (2006.01); H04L 27/26 (2006.01); H04W 56/00 (2009.01); H04W 48/12 (2009.01); H04W 72/0453 (2023.01); H04W 88/08 (2009.01); H04W 88/02 (2009.01); H04W 72/20 (2023.01);
U.S. Cl.
CPC ...
H04L 27/266 (2013.01); H04L 5/0007 (2013.01); H04L 27/2657 (2013.01); H04L 27/2666 (2013.01); H04W 48/12 (2013.01); H04W 56/001 (2013.01); H04W 72/0453 (2013.01); H04W 72/20 (2023.01); H04W 88/02 (2013.01); H04W 88/08 (2013.01);
Abstract

Configuring control information comprises determining a frequency offset including an RB and RE level frequency offset, where the frequency offset is determined based on a lowest RE of an SS/PBCH block and a lowest RE of CORESET for RMSI, jointly configuring, using a first field of 4 bits, the RB level frequency offset with a multiplexing pattern of the SS/PBCH block and the CORESET, a BW of the CORESET, and a number of symbols for the CORESET for a combination of a SCS of the SS/PBCH block and a SCS of the CORESET, configuring using a second field of the 4 bits generating an MIB including the RB level frequency offset and the RE level frequency offset; and transmitting, to a UE, the MIB over a PBCH.


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