The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2024

Filed:

Apr. 13, 2021
Applicants:

Ordos Yuansheng Optoelectronics Co., Ltd., Inner Mongolia, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Yongbo Ju, Beijing, CN;

Pengfei Cui, Beijing, CN;

Jian Sun, Beijing, CN;

Deshuai Wang, Beijing, CN;

Xiangkai Shen, Beijing, CN;

Jianbin Gao, Beijing, CN;

Jiannan Wang, Beijing, CN;

Guangshuai Wang, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1345 (2006.01); H01L 27/12 (2006.01); G06F 3/044 (2006.01); G06F 3/041 (2006.01); G02F 1/1333 (2006.01); H01L 23/00 (2006.01); G02F 1/1368 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1244 (2013.01); G02F 1/13338 (2013.01); G02F 1/13458 (2013.01); G06F 3/0412 (2013.01); G06F 3/0445 (2019.05); G06F 3/04164 (2019.05); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 27/1259 (2013.01); G02F 1/13452 (2013.01); G02F 1/13685 (2021.01); G06F 2203/04103 (2013.01); H01L 24/06 (2013.01); H01L 2224/0345 (2013.01); H01L 2224/0362 (2013.01); H01L 2224/03614 (2013.01); H01L 2224/05008 (2013.01); H01L 2224/05013 (2013.01); H01L 2224/0518 (2013.01); H01L 2224/05073 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05138 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05548 (2013.01); H01L 2224/05553 (2013.01); H01L 2224/05566 (2013.01); H01L 2224/05573 (2013.01); H01L 2224/05686 (2013.01); H01L 2224/06165 (2013.01); H01L 2924/0106 (2013.01); H01L 2924/0132 (2013.01); H01L 2924/0549 (2013.01);
Abstract

An array substrate has a display area and a bonding area located on a side of the display area. The array substrate includes a base, a plurality of first transistors, a plurality of conductive pins and a plurality of conductive electrodes. The plurality of first transistors are disposed on a side of the base and located in the display area; a first transistor includes a first gate, a first source and a first drain. The plurality of conductive pins are disposed on the side of the base and located in the bonding area, and are disposed in a same layer as the first gate. The plurality of conductive electrodes are each disposed on a respective one of surfaces of the plurality of conductive pins away from the base.


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