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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11901321 B1

PDFFull Text
Date of Patent:
Feb. 13, 2024

Filed:

Jun. 30, 2022

Three-dimensional (3d) storage device using wafer-to-wafer bonding

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Eun Chu Oh, Hwaseong-si, KR;

Junyeong Seok, Seoul, KR;

Younggul Song, Hwaseong-si, KR;

Byungchul Jang, Suwon-si, KR;

Joonsung Lim, Seongnam-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Gyeonggi-do, KR;

Attorney:

Harness, Dickey & Pierce, P.L.C.

Primary Examiner:

John J Tabone, Jr

Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); G06F 11/10 (2006.01); H01L 25/00 (2006.01); G11C 7/10 (2006.01); H10B 41/20 (2023.01); H10B 41/40 (2023.01); H10B 41/50 (2023.01); H10B 43/20 (2023.01); H10B 43/40 (2023.01); H10B 43/50 (2023.01);
U.S. Cl.
CPC ...
H01L 24/08 (2013.01); G06F 11/1008 (2013.01); G06F 11/1048 (2013.01); G11C 7/10 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H10B 41/20 (2023.02); H10B 41/40 (2023.02); H10B 41/50 (2023.02); H10B 43/20 (2023.02); H10B 43/40 (2023.02); H10B 43/50 (2023.02); H01L 2224/0603 (2013.01); H01L 2224/08145 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01);
Abstract

A three-dimensional (3D) storage device using wafer-to-wafer bonding is disclosed. In the storage device, a first chip including a peripheral circuit region including a first control logic circuit configured to control operation modes of a nonvolatile memory (NVM) device is wafer-bonded with a second chip including 3D arrays of NVM cells, and a memory controller includes a third chip including a control circuit region. The control circuit region of the third chip includes a second control logic circuit associated with operation conditions of the NVM device, and the second control logic circuit includes a serializer/deserializer (SERDES) interface configured to share random access memory (RAM) in the memory controller and transmit and receive data to and from the NVM device.

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