The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 13, 2024
Filed:
Jun. 30, 2022
Applicant:
Rohm Co., Ltd., Kyoto, JP;
Inventor:
Kunihiro Komiya, Kyoto, JP;
Assignee:
ROHM CO., LTD, Ukyo-Ku, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 23/50 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3114 (2013.01); H01L 23/50 (2013.01); H01L 23/528 (2013.01); H01L 23/53214 (2013.01); H01L 23/53228 (2013.01); H01L 23/53242 (2013.01); H01L 24/06 (2013.01); H01L 24/10 (2013.01); H01L 24/13 (2013.01); H01L 24/14 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05144 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05644 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/0612 (2013.01); H01L 2224/13 (2013.01); H01L 2224/13023 (2013.01); H01L 2224/13025 (2013.01); H01L 2224/13099 (2013.01); H01L 2224/1413 (2013.01); H01L 2224/14104 (2013.01); H01L 2924/014 (2013.01); H01L 2924/01005 (2013.01); H01L 2924/01006 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/01082 (2013.01); H01L 2924/14 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/30107 (2013.01);
Abstract
The semiconductor device has the CSP structure and may include a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps may be arranged in two rows along the periphery of the semiconductor device. The electrode pads may be arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring may be extended from an electrode pad and may be connected to any one of the outermost solder bumps or any one of the inner solder bumps.