The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2024

Filed:

Feb. 24, 2022
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventor:

Akinori Bito, Yokohama Kanagawa, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 (2006.01); G11C 7/10 (2006.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01); H03K 19/17736 (2020.01);
U.S. Cl.
CPC ...
G11C 7/1066 (2013.01); G06F 13/1668 (2013.01); G06F 13/4068 (2013.01); G11C 7/1093 (2013.01); H03K 19/17744 (2013.01);
Abstract

A memory system includes a nonvolatile memory, and a controller including an equalizer circuit and a clock-and-data output circuit. The equalizer circuit receives a first data signal from a host via a serial communication, reduces an inter-symbol interference jitter of the first data signal to generate a second data signal, and outputs the second data signal. The clock-and-data output circuit extracts a third data signal and a clock signal from the second data signal and outputs the third data signal and the clock signal. The controller executes, when a link speed with the host is switched, a process of detecting predetermined data in the third data signal based on the first data signal received from the host, and resets a state of the clock-and-data output circuit when the predetermined data is not detected within a predetermined period of time.


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