The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2024

Filed:

Aug. 13, 2020
Applicant:

Sony Semiconductor Solutions Corporation, Kanagawa, JP;

Inventor:

Yusuke Shuto, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/413 (2006.01); G11C 11/412 (2006.01); G11C 11/16 (2006.01); H03K 3/037 (2006.01);
U.S. Cl.
CPC ...
G11C 11/413 (2013.01); G11C 11/412 (2013.01); G11C 11/1697 (2013.01); H03K 3/037 (2013.01);
Abstract

A semiconductor circuit according to the present disclosure includes: a first circuit configured to apply an inverted voltage of a voltage at a first node to a second node; a second circuit configured to apply an inverted voltage of a voltage at a second node to the first node; a first storage element including first, second, and third terminals; a first transistor including a drain coupled to the first node and a source coupled to the first terminal of the first storage element; a second transistor including a gate coupled to the first node or the second node and a drain coupled to the second terminal of the first storage element; and a third transistor including a gate coupled to the first node or the second node and a drain coupled to the second terminal of the first storage element. The first storage element is configured to set a resistance state between the first terminal and the second and third terminals in accordance with a direction of a current flowing between the second and third terminals.


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