The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2024

Filed:

Mar. 31, 2022
Applicant:

Dreambig Semiconductor Inc., San Jose, CA (US);

Inventors:

Sohail A Syed, San Jose, CA (US);

Hillel Gazit, Palo Alto, CA (US);

Hon Luu, San Jose, CA (US);

Pranab Ghosh, Pleasonton, CA (US);

Assignee:

DreamBig Semiconductor Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 9/455 (2018.01);
U.S. Cl.
CPC ...
G06F 3/0664 (2013.01); G06F 3/0604 (2013.01); G06F 3/0673 (2013.01); G06F 9/45558 (2013.01); G06F 2009/45583 (2013.01);
Abstract

A content addressable memory circuit comprising: a memory device array including multiple memory devices coupled for simultaneous access to memory address locations that share a common memory address; multiple virtual modules (VMs), wherein each VM stores a data set that includes key values stored within an assigned memory address range within the memory array that are assigned to the VM; wherein each VM, stores a virtual hash table in non-transitory memory, that associates hash values with memory addresses within an assigned memory address range of the VM; hash logic is operable to determine a hash value, based upon a received key value and a respective assigned memory address range; and memory controller logic is operable to use a virtual hash table to access a memory address in an assigned memory address range, based upon the determined hash value.


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