The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2024

Filed:

Jun. 03, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jaewon Park, Hwaseong-si, KR;

Sangkil Park, Hwaseong-si, KR;

Jaehoon Lee, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0653 (2013.01); G06F 3/0614 (2013.01); G06F 3/0679 (2013.01);
Abstract

A method of testing a memory device, a memory built-in self-test (MBIST) circuit, and a memory device for improving reliability and reducing a test time. The memory device includes a plurality of memory banks and the MBIST circuit. The MBIST circuit is configured to generate double data rate (DDR) test patterns and parallel bit test (PBT) test patterns to test the memory banks. When a defective cell is detected as a result of the PBT test or the DDR test, the MBIST circuit is configured to perform a repair operation for replacing the defective cell with a redundancy cell and perform a re-test to verify the repair operation. The MBIST circuit may be configured to perform the DDR test on one or more memory cells including the defective cell during the re-test.


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