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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11899862 B1

PDFFull Text
Date of Patent:
Feb. 13, 2024

Filed:

Nov. 10, 2020

Display panel and display apparatus including the same

Applicant:

Samsung Display Co., Ltd., Yongin-si, KR;

Inventors:

Seunglyong Bok, Yongin-si, KR;

Yongje Jeon, Yongin-si, KR;

Songi Kim, Yongin-si, KR;

Okkyung Park, Yongin-si, KR;

Youngran Son, Yongin-si, KR;

Dongho Lee, Yongin-si, KR;

Seunghoon Lee, Yongin-si, KR;

Assignee:

SAMSUNG DISPLAY CO., LTD., Yongin-si, KR;

Attorney:

KILE PARK REED & HOUTTEMAN PLLC

Primary Examiner:

Brian M Butcher

Int. Cl.
CPC ...
G06F 3/041 (2006.01); G06F 1/16 (2006.01); G09G 3/3233 (2016.01); G06F 3/044 (2006.01); H04N 23/55 (2023.01); H10K 50/858 (2023.01); H10K 50/842 (2023.01); H10K 59/38 (2023.01); H10K 59/40 (2023.01); H10K 59/121 (2023.01); H10K 59/125 (2023.01); H10K 77/10 (2023.01);
U.S. Cl.
CPC ...
G06F 3/0412 (2013.01); G06F 1/1626 (2013.01); G06F 3/0443 (2019.05); G06F 3/0446 (2019.05); G09G 3/3233 (2013.01); H04N 23/55 (2023.01); H10K 50/8426 (2023.02); H10K 50/858 (2023.02); H10K 59/121 (2023.02); H10K 59/125 (2023.02); H10K 59/38 (2023.02); H10K 59/40 (2023.02); H10K 77/111 (2023.02);
Abstract

A display panel includes a main display area, and a component area including a transmission area. The display panel includes a substrate including a groove disposed in the transmission area in a depth direction of the substrate; main display elements disposed above the substrate in the main display area; main pixel circuits electrically connected to the main display elements; and auxiliary display elements disposed above the substrate in the component area; and auxiliary pixel circuits electrically connected to the auxiliary display elements.

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