The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 13, 2024
Filed:
Nov. 18, 2019
Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;
Keita Sato, Sagamihara, JP;
Yuto Yakubo, Atsugi, JP;
Yoshiaki Oikawa, Atsugi, JP;
Shunpei Yamazaki, Setagaya, JP;
Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;
Abstract
A low-power semiconductor device is provided. A retention transistor is provided between a control circuit and an output transistor. An output terminal of the control circuit is electrically connected to one of a source and a drain of the retention transistor, and the other of the source and the drain of the retention transistor is electrically connected to a gate of the output transistor. A node to which the other of the source and the drain of the retention transistor and the gate of the output transistor are electrically connected is a retention node. When the retention transistor is in an on state, a potential corresponding to a potential output from the control circuit is written to the retention node. Then, when the retention transistor is in an off state, the potential of the retention node is retained. Thus, a gate potential of the output transistor can be kept at a constant value even when the control circuit is off. Accordingly, even when the control circuit is off, a constant potential can be continuously output from one of a source and a drain of the output transistor, for example.