The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2024

Filed:

Jul. 15, 2022
Applicant:

Hewlett Packard Enterprise Development Lp, Houston, TX (US);

Inventors:

Naysen J. Robertson, Orangevale, CA (US);

Christopher M. Wesneski, The Colony, TX (US);

Samuel Gonzalez, Tomball, TX (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3185 (2006.01); G06F 30/34 (2020.01); G01R 31/317 (2006.01);
U.S. Cl.
CPC ...
G01R 31/3185 (2013.01); G06F 30/34 (2020.01); G01R 31/31727 (2013.01);
Abstract

In some examples, a computing device includes a first reset domain including a test controller and a configurable test logic. The computing device includes a second reset domain including a subsystem to be measured by the configurable test logic. The first reset domain is to enter a reset mode, and after exiting the reset mode, receive configuration information that configures the configurable test logic. The test controller of the first reset domain is to maintain the second reset domain in a reset mode after the first reset domain has exited the reset mode of the first reset domain, and responsive to the received configuration information for configuring the configurable test logic, provide a reset release indication to the second reset domain to allow the second reset domain to exit the reset mode of the second reset domain.


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