The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 06, 2024
Filed:
Sep. 20, 2019
Applicant:
Proterial, Ltd., Tokyo, JP;
Inventor:
Takahiro Umeyama, Mie, JP;
Assignee:
HITACHI METALS, LTD., Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/18 (2006.01); G01L 9/00 (2006.01); G01L 9/04 (2006.01); G01L 19/14 (2006.01); G05D 7/06 (2006.01); H05K 1/11 (2006.01); H05K 3/32 (2006.01);
U.S. Cl.
CPC ...
H05K 1/189 (2013.01); G01L 9/0041 (2013.01); G01L 9/04 (2013.01); G01L 19/141 (2013.01); G05D 7/06 (2013.01); H05K 1/115 (2013.01); H05K 1/181 (2013.01); H05K 3/323 (2013.01); H05K 2201/09372 (2013.01); H05K 2201/09836 (2013.01); H05K 2201/10151 (2013.01);
Abstract
In a flexible printed wiring board (), a first electrical conduction pattern () prepared on the first surface () on which a bare chip () is mounted is prepared only inside a mounting region () of the bare chip. Preferably, the first electrical conduction patterns () are prepared so as to avoid positions opposite to test electrodes () which the bare chip comprises. Thereby, in the flexible printed wiring board used for mounting the bare chip, occurrence of malfunction resulting from electrical connection with a part other than a bump of the bare chip can be certainly prevented, and reliability of various devices using the bare chip can be improved.