Timing precision maintenance with reduced power during system sleep

Abstract

Embodiments of the present disclosure provide systems and methods for maintaining timing precision in different operating modes of a device (e.g., a wireless node). A timing circuit may switch clock signals between two different modes (e.g., high power and low power) while preserving timing precision. In a high-power mode, the timing circuit may provide a high frequency clock signal, and in a lower-power mode, it may provide a low frequency clock signal. Moreover, the switching between the different clock signals may be synchronized to select edges of the low frequency clock signal.