The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 06, 2024

Filed:

Mar. 27, 2019
Applicant:

Dowa Electronics Materials Co., Ltd., Tokyo, JP;

Inventors:

Yuta Koshika, Akita, JP;

Yoshitaka Kadowaki, Akita, JP;

Tetsuya Ikuta, Akita, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/00 (2010.01); H01L 33/60 (2010.01); H01L 33/30 (2010.01);
U.S. Cl.
CPC ...
H01L 33/60 (2013.01); H01L 33/0066 (2013.01); H01L 33/30 (2013.01); H01L 2933/0058 (2013.01);
Abstract

A method of manufacturing a semiconductor optical device of this disclosure includes the steps of forming an etch stop layer on an InP growth substrate, the etch stop layer having a thickness of 100 nm or less; and forming a semiconductor laminate on the etch stop layer by stacking a plurality of InGaAsP-based III-V group compound semiconductor layers containing at least In and P. Further, an intermediate article of a semiconductor optical device of the present disclosure includes an InP growth substrate; an etch stop layer formed on the InP growth substrate, the etch stop layer having a thickness of 100 nm or less; and a semiconductor laminate formed on the etch stop layer, including a plurality of InGaAsP-based III-V group compound semiconductor layers containing at least In and P stacked one another.


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