The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 06, 2024

Filed:

Dec. 22, 2020
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Dongbing Shao, Briarcliff Manor, NY (US);

Chen Zhang, Guilderland, NY (US);

Zheng Xu, Wappingers Falls, NY (US);

Tenko Yamashita, Schenectady, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 21/822 (2006.01); H01L 23/50 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 21/8234 (2006.01); H10B 41/20 (2023.01); H10B 51/20 (2023.01);
U.S. Cl.
CPC ...
H01L 23/5286 (2013.01); H01L 21/8221 (2013.01); H01L 21/823475 (2013.01); H01L 21/823871 (2013.01); H01L 23/50 (2013.01); H01L 27/092 (2013.01); H10B 41/20 (2023.02); H10B 51/20 (2023.02);
Abstract

A semiconductor structure includes a three-dimensional stacked transistor structure including first and second field-effect transistors of a first type at a first vertical level and third and fourth field-effect transistors of a second type at a second vertical level disposed over the first vertical level. The semiconductor structure also includes a first gate structure shared between the first and second field-effect transistors at the first vertical level, a second gate structure shared between the third and fourth field-effect transistors at the second vertical level, and a gate contact shared by the first and second gate structures. The wherein the first and second gate structures are vertically aligned with another in a layout of the three-dimensional stacked transistor structure between source drain/regions of the first, second, third and fourth field-effect transistors.


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