The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 06, 2024

Filed:

Mar. 23, 2022
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Yaron Freiman, Tel-Mond, IL;

Noam Jungmann, Holon, IL;

Tomer Abraham Cohen, Binyamina, IL;

Elazar Kachir, Tel Aviv, IL;

Hezi Shalom, Tel Aviv, IL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G11C 29/44 (2006.01); G06F 11/16 (2006.01); G06F 11/14 (2006.01); G06F 11/20 (2006.01); G06F 11/07 (2006.01); G11C 11/418 (2006.01);
U.S. Cl.
CPC ...
G11C 29/4401 (2013.01); G06F 11/073 (2013.01); G06F 11/0793 (2013.01); G06F 11/141 (2013.01); G06F 11/1666 (2013.01); G06F 11/2043 (2013.01); G11C 11/418 (2013.01);
Abstract

A system, program product, and method for processing synchronized memory repairs. The method includes identifying a faulty memory row from a plurality of functioning memory rows in a memory array. The method also includes executing memory row repair operations directed toward the faulty memory row and identifying a repair row to operationally replace the faulty memory row. The method also includes creating a multiple hot state within a memory decoder. The memory decoder includes logic circuitry for executing operation of the plurality of functioning memory rows. The method further includes activating a wordline of the identified repair row through the multiple hot state, and executing one or more memory operations on the identified repair row though the memory decoder. Accordingly, the embodiments disclosed herein facilitate synchronization of the repair row and functioning memory rows within the memory array, as well as any associated peripheral signals.


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