The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 06, 2024
Filed:
Apr. 12, 2022
Stmicroelectronics S.r.l., Agrate Brianza, IT;
Alma Mater Studiorum-universita' Di Bologna, Bologna, IT;
Marco Pasotti, Travaco' Siccomario, IT;
Marcella Carissimi, Bergamo, IT;
Alessio Antolini, Bologna, IT;
Eleonora Franchi Scarselli, Bologna, IT;
Antonio Gnudi, Bologna, IT;
Andrea Lico, Polia, IT;
Paolo Romele, Impington, GB;
STMicroelectronics S.r.l., Agrate Brianza, IT;
Alma Mater Studiorum—Universita' Di Bologna, Bologna, IT;
Abstract
An in-memory computation (IMC) circuit includes a memory array formed by memory cells arranged in row-by-column matrix. Computational weights for an IMC operation are stored in the memory cells. Each column includes a bit line connected to the memory cells. A biasing circuit is connected between each bit line and a corresponding column output. A column combining circuit combines and integrates analog signals at the column outputs of the biasing circuits. Each biasing circuit operates to apply a fixed reference voltage level to its bit line. Each biasing circuit further includes a switching circuit that is controlled to turn on for a time duration controlled by asps comparison of a coefficient data signal to a ramp signal to generate the analog signal dependent on the computational weight. The ramp signal is generated using a reference current derived from a reference memory cell.