The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 06, 2024

Filed:

Oct. 11, 2021
Applicant:

Edgecortix Inc., Tokyo, JP;

Inventors:

Nikolay Nez, Tokyo, JP;

Hamid Reza Zohouri, Sunnyvale, CA (US);

Oleg Khavin, Tokyo, JP;

Antonio Tomas Nevado Vilchez, Tokyo, JP;

Sakyasingha Dasgupta, Tokyo, JP;

Assignee:

EDGECORTIX INC., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01N 33/48 (2006.01); G01N 33/50 (2006.01); G06N 3/063 (2023.01); G06F 12/02 (2006.01); G06F 17/15 (2006.01); G06N 5/04 (2023.01);
U.S. Cl.
CPC ...
G06N 3/063 (2013.01); G06F 12/0238 (2013.01); G06F 17/15 (2013.01); G06N 5/04 (2013.01);
Abstract

Neural network inference may be performed by configuration of a device including an accumulation memory, a plurality of convolution modules configured to perform mathematical operations on input values, a plurality of adder modules configured to sum values output from the plurality of convolution modules, and a plurality of convolution output interconnects connecting the plurality of convolution modules, the plurality of adder modules, and the accumulation memory. The accumulation memory is an accumulation memory allocation of a writable memory block having a reconfigurable bank width, and each bank of the accumulation memory allocation is a virtual combination of consecutive banks of the writable memory block.


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