The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 06, 2024

Filed:

Oct. 12, 2021
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

Daniel Joseph Linnen, Naperville, IL (US);

Ariel Navon, Revava, IL;

Alexander Bazarsky, Holon, IL;

Ofir Pele, Hod Hasharon, IL;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 11/10 (2006.01); G06N 3/10 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0619 (2013.01); G06F 3/0658 (2013.01); G06F 3/0685 (2013.01); G06F 11/1012 (2013.01); G06N 3/10 (2013.01);
Abstract

Recurrent Neural Networks (RNNs) wherein a non-volatile memory (NVM) array provides a memory bank for the RNN. The RNN may include a Neural Turning Machine (NTM) and the memory bank may be an NTM matrix stored in the NVM array. In some examples, a data storage device (DSD) that controls the NVM array includes both a data storage controller and a separate NTM controller. The separate NTM controller accesses the NTM matrix of the NVM array directly while bypassing flash translation layer (FTL) components of the data storage controller. Additionally, various majority wins error detection and correction procedures are described, as well as various disparity count-based procedures.


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