The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 06, 2024
Filed:
Jul. 21, 2022
Silicon Tailor Limited, London, GB;
Paul James Metzgen, London, GB;
Silicon Tailor Limited, Putney, GB;
Abstract
A circuit having multiple inputs and multiple outputs the circuit being for switching signals received at any of the inputs to any of the outputs, the circuit comprising: a first switch matrix, the first switch matrix being capable of directing signals received at the inputs of the circuit to multiple first intermediate ports; a second switch matrix, the second switch matrix being capable of directing signals received at multiple second intermediate ports to multiple third intermediate ports, the number of the second intermediate ports being less than the number of the inputs of the circuit; one or more primary bypass links, each primary bypass link being capable of coupling one or more of the first intermediate ports to a respective one or more of the outputs of the circuit independently of the second switch matrix; a first redirection layer, the first redirection layer being capable of, for each first intermediate port, directing a signal received at that first intermediate port to a primary bypass link or to a second intermediate port; and a second redirection layer, the second redirection layer being capable of directing signals received at each of the primary bypass links to a respective one or more outputs of the circuit, and directing signals received at each of the third intermediate ports to a respective one or more outputs of the circuit.